Voltage divider

A voltage divider is two impedances in series across a source, with the output taken at their junction. For two resistors $R_1$ (top, next to the input) and $R_2$ (bottom, to ground) with input $v_{in}$ applied across the pair and output $v_{out}$ taken across $R_2$:

$v_{out}=v_{in}\frac{R_2}{R_1+R_2}$

Why this is true

The same current flows through both resistors because they are in series (and, assuming nothing is drawn from the output node, that current is not diverted). By Ohm’s law that current is $i=v_{in}/(R_1+R_2)$. The output voltage is just the drop across $R_2$:

$v_{out}=i{R}_2=v_{in}\frac{R_2}{R_1+R_2}$

The ratio $R_2/(R_1+R_2)$ is always between $0$ and $1$, so a divider only ever attenuates. The input voltage splits between the two resistors in proportion to their resistances; the larger resistor gets the larger share. Make $R_2\gg R_1$ and almost all of $v_{in}$ appears at the output; make $R_2\ll R_1$ and almost none does.

Generalises to impedances

Replace resistors with complex impedances $Z_1,Z_2$ (using $Z_C=1/(j\omega C)$ for a capacitor, $Z_L=j\omega L$ for an inductor) and the rule is identical:

$v_{out}=v_{in}\frac{Z_2}{Z_1+Z_2}$

Because the $Z$‘s are frequency-dependent, the division ratio now depends on frequency. That is how an RC lowpass filter works: R on top, C on the bottom, and at high frequency $Z_C\to 0$ so the output is divided away. The phasor convention $e^{j\omega t}$ makes this a one-line derivation.

Why it is everywhere

The voltage divider is the most reused building block in this material. Thévenin/source resistance forming a divider with a load is the loading effect that motivates the Buffer amplifier. RC filters are frequency-dependent dividers. Transistor bias networks set a gate or base DC voltage with a resistor divider. In the Difference amplifier the non-inverting input is a divider tap $v_{I2}{R}_4/(R_3+R_4)$, and the "$1+R_2/R_1$" of the Non-inverting amplifier (op-amp) is the divider relation solved backwards. Spot the divider, write the ratio, and a large fraction of circuit analysis falls out. One caveat: the simple formula assumes the output node draws no current. If a load is connected there, fold it in (e.g. $R_2\parallel R_L$) or buffer the tap.