2's Complement Arithmetic

2’s complement is the dominant representation for signed binary integers in modern hardware. To negate a number, invert every bit and add $1$. The same adder circuit handles addition and subtraction across all sign combinations — no special cases, no end-around carry.

For an $n$-bit number $N$, the 2’s complement is $2^n-N$. Equivalently, the 1’s complement plus one. See Radix Complement for the general theory; 2’s complement is the radix complement in base $2$.

Examples for 8-bit:

• $+25=00011001$
• $-25=11100111$ (invert all bits → $11100110$, add 1 → $11100111$)

The MSB still indicates sign — $0$ for positive, $1$ for negative — but it also carries place value. In an $n$-bit 2’s complement number, the MSB contributes $-2^{n-1}$ rather than $+2^{n-1}$. So the value of $b_{n-1}{b}_{n-2}\dots b_0$ is

$-b_{n-1}\cdot 2^{n-1}+{\sum }_{i=0}^{n-2}{b}_i\cdot 2^i$

Range for $n$ bits: $-2^{n-1}$ to $+2^{n-1}-1$ — asymmetric, with one more negative value than positive.

Why it wins

Three properties make 2’s complement the obvious choice:

1. One zero. $0000\dots 0$ is the only zero — no $+0$ vs. $-0$ ambiguity.
2. Standard addition for all sign combinations. Just add the bits including the sign positions, and discard any carry out of the MSB. The result is correct.
3. Same hardware as unsigned addition. A 2’s complement adder is electrically identical to an unsigned adder — only the interpretation of the bits differs.

Addition

No special cases. Add the bits, throw away the carry out of the MSB:

$11111010+11110011=\cancel{1}11101101$

If those operands are $-6$ and $-13$, the result $11101101$ is the 2’s complement representation of $-19$. Verify: invert and add 1 → $00010010+1=00010011=19$, so $11101101=-19$. ✓

Subtraction

Subtract by adding the 2’s complement of the subtrahend:

$13-6=13+(-6)$

$00001101+11111010=\cancel{1}00000111=7$

Discard the MSB carry; result is $7$.

Implementation: adder/subtractor

A 2’s complement adder/subtractor uses one adder plus a row of XOR gates controlled by a Sub bit. The $n$-bit operand $A$ feeds the adder’s $A$ inputs directly; operand $B$ feeds through $n$ XOR gates whose other input is the shared Sub line, with the XOR outputs feeding the adder’s $B$ inputs; Sub also feeds the adder’s carry-in.

When Sub $=0$: the XORs pass $B$ through unchanged, $C_{in}=0$, and the circuit computes $A+B$.

When Sub $=1$: the XORs invert $B$, and Sub also feeds $C_{in}$. The result is $A+\overline{B}+1=A+(-B)=A-B$.

The XOR-with-control-bit pattern is exactly the “controlled inverter” use of XOR. Combined with the adder, you get an addition/subtraction unit at minimal extra hardware cost.

Overflow

Adding two same-signed 2’s complement numbers can give a result whose sign bit doesn’t match — the value overflowed the representable range. See Overflow (binary arithmetic).

Quick conversion

To negate a 2’s complement number by hand:

1. Find the rightmost $1$ in the bit pattern.
2. Leave it and everything to its right unchanged.
3. Invert everything to its left.

Example: negate $00101100$. Rightmost $1$ is at bit 2. Leave bits 0–2 ($100$) alone, invert bits 3–7 ($00010\to 11101$). Result: $11010100$. Check: $00101100=+44$ and $11010100=-44$. ✓