Fan-in

Fan-in is the number of inputs a logic gate has. A 2-input AND has fan-in $2$; a 4-input OR has fan-in $4$. (The related metric fan-out counts how many gate inputs a single output drives.)

Fan-in matters because real gates can’t be made arbitrarily wide. As you add more inputs to a single CMOS gate, several things get worse:

• Propagation delay grows. Each input adds capacitance to the gate node; charging or discharging more capacitance takes longer. A 6-input NAND is noticeably slower than a 2-input NAND.
• Power consumption rises. More transistors switching, more dynamic power dissipated.
• Noise margins shrink. Series transistor stacks (NMOS in the pull-down for NAND, PMOS in the pull-up for NOR) have higher resistance, dragging the output more weakly toward the rail.
• Fabrication limits hit. Many process technologies and FPGA cells cap fan-in around 4 to 6.

So if you need a 12-input AND, you don’t build it as one gate. You decompose it.

Gate decomposition

Split a high-fan-in function across multiple smaller-fan-in gates arranged in stages. A 12-input AND becomes, say, four 3-input ANDs feeding a 4-input AND — two stages of fan-in $\le 4$.

Algebraically:

$x_1{x}_2\dots x_{12}=(x_1{x}_2{x}_3)(x_4{x}_5{x}_6)(x_7{x}_8{x}_9)(x_{10}{x}_{11}{x}_{12})$

Each parenthesized group is one 3-input AND; the four results feed a 4-input AND.

The cost: an extra level of gate delay. The benefit: each individual gate is fast and reliable.

This is the entry point to Multilevel synthesis — the deliberate trade of two-level minimization for more levels of smaller gates.

Buffers

When a single output has too many destinations (high fan-out), the same gate has to drive too much capacitance and slows down. The fix is to insert a buffer — a gate that just passes its input through (typically two NOT gates in series) to restore signal strength. The buffer’s input is just one load on the original driver; its output drives the heavy load instead.

Buffers don’t change the logic, just the electrical drive. Useful for clock distribution (a clock signal that needs to fan out to thousands of flip-flops) and for crossing long wires between sections of a chip.