Full-adder

A full-adder adds three input bits — two operands $A$, $B$, and a carry-in $C_{in}$ from the column to the right — and produces a sum $S$ and a carry-out $C_{out}$. It’s the bit-slice you cascade $n$ times to build an $n$-bit adder (the ripple-carry design wires the $C_{out}$ of stage $i$ into the $C_{in}$ of stage $i+1$).

The contrast with a half-adder is the third input. The half-adder ignores any incoming carry and so can only handle bit 0. The full-adder folds the incoming carry in and so works in every column.

Truth table

Eight rows, one per combination of $A$, $B$, $C_{in}$:

Two patterns to read off:

• $S=1$ exactly when an odd number of the three inputs are $1$ (one or three of them). That’s three-input XOR.
• $C_{out}=1$ exactly when at least two of the three inputs are $1$. That’s the majority function of three inputs.

Boolean expressions

$S=A\oplus B\oplus C_{in}$

$C_{out}=AB+C_{in}(A\oplus B)$

The carry-out form $AB+C_{in}(A\oplus B)$ is convenient because it shares the $A\oplus B$ subexpression with the sum, so the gate that computes $S$ also helps compute $C_{out}$. Equivalently you can write the carry-out as the symmetric sum-of-products

$C_{out}=AB+A{C}_{in}+B{C}_{in}$

which is more obviously the “any two of three” majority. Either form is fine; the choice is about gate count and routing.

Circuit

A direct two-level implementation uses XOR/AND/OR gates straight from the equations.

Built from two half-adders

A full-adder is naturally built from two half-adders plus one OR gate. The first half-adder adds $A$ and $B$, producing a partial sum $S_1=A\oplus B$ and a partial carry $C_1=AB$. The second half-adder adds $S_1$ and $C_{in}$, producing the final sum $S=S_1\oplus C_{in}=A\oplus B\oplus C_{in}$ and a second partial carry $C_2=S_1{C}_{in}=(A\oplus B)C_{in}$. The final carry-out is

$C_{out}=C_1+C_2=AB+(A\oplus B)C_{in}$

— exactly the equation above.

Decomposed view, showing every gate inside the two half-adders:

This decomposition is mostly pedagogical (it shows where the formula comes from). In real silicon you’d implement the full-adder as a single optimised cell.

Latency in a ripple-carry chain

In an $n$-bit ripple-carry adder, the carry has to propagate through every full-adder in turn before the answer is valid. If a full-adder has carry latency $t_c$, the total worst-case delay is roughly $n\cdot t_c$. That linear scaling is the motivation for the carry-lookahead adder, which computes the carries in parallel from the inputs.