VHDL

VHDL (VHSIC Hardware Description Language) is a text-based language for describing digital hardware. Unlike a programming language, VHDL describes what hardware looks like (gates, signals, registers) and a synthesis tool turns that description into actual logic on a chip or FPGA.

Every VHDL design has two parts: an entity (the interface, what signals come in and out) and an architecture (the implementation, what the circuit does inside).

Library and use clauses

Most digital projects start with the standard logic definitions:

library ieee;
use ieee.std_logic_1164.all;

This pulls in std_logic, the standard 9-value type: $\text{’U’}$ uninitialized, $\text{’X’}$ strong unknown, $\text{’0’}$ and $\text{’1’}$ strong drives, $\text{’Z’}$ high-impedance, $\text{’W’}$ weak unknown, $\text{’L’}$ and $\text{’H’}$ weak drives, and $\text{’-’}$ don’t-care. Without it, you only have raw bit (just $0$ and $1$), which can’t model real hardware behaviors like tri-state buses or undefined startup.

Entity and architecture

A VHDL design is split into two parts: the VHDL entity (interface, input/output ports) and the VHDL architecture (implementation, what the block does internally). The entity is the “what”, the function signature; the architecture is the “how.”

The architecture body uses signal assignments (<=) to describe the output logic. Multiple assignments execute concurrently; there’s no notion of order, because they describe parallel hardware. Internal wires are declared as signal in the architecture’s declarative section.

Worked example: full-adder

The Full-adder takes inputs $x,y$, and a carry-in $C_{in}$, producing sum $s$ and carry-out $C_{out}$.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY fulladd IS
    PORT (Cin, x, y : IN  STD_LOGIC;
          s, Cout    : OUT STD_LOGIC);
END fulladd;
 
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
    s    <= x XOR y XOR Cin;
    Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y);
END LogicFunc;

Both outputs are written in terms of the inputs using Boolean expressions. The synthesis tool sees this and infers two-level AND-OR logic for Cout and an XOR tree for s.

Style notes

• VHDL is case-insensitive: AND, and, And are all the same.
• Comments start with -- and run to the end of line.
• The entity and end entity (and similarly for architecture) names must match.
• Get the syntax right. Synthesis tools and simulators are picky about semicolons, port-list parentheses, and the IS/BEGIN/END skeleton. A missing semicolon usually produces a confusing error message far from where the actual mistake is.

VHDL targets FPGAs and ASICs both. The same VHDL source compiles to different gate-level netlists depending on the target technology; the tool maps logic to whatever primitives are available (LUTs in FPGAs, standard cells in an ASIC).