VHDL entity

A VHDL entity declares the interface of a digital circuit block — its input and output ports — without saying anything about how the block is implemented internally. Think of it as the function signature: the entity tells you what signals come in and out, not what the block does with them. The actual logic lives in a separate VHDL architecture paired with the entity.

Every VHDL design has at least one entity. A larger design has many entities, each describing a sub-block, and they instantiate each other.

Syntax

entity example2 is
    port (
        x1, x2, x3, x4 : in  std_logic;
        f, g           : out std_logic
    );
end entity example2;

The port clause lists every input and output. Each port has:

• A name (x1, f, etc.).
• A direction — in, out, or inout.
• A type — std_logic, std_logic_vector, bit, integer, etc.

The entity name (example2) is repeated at the end entity example2; line for readability.

Port directions

• in — signal flows from outside into the block.
• out — signal flows from the block to the outside.
• inout — bidirectional. Used for tri-state buses; rare in straightforward synchronous designs.
• buffer — output that can also be read inside the architecture. Avoid in modern code: buffer ports propagate their resolution restrictions up the hierarchy (every instantiator of this entity must use a buffer port too, which is rarely what you want) and only allow a single driver. The standard idiom is to declare an internal signal, drive it from logic, and connect it to a plain out port — same effect without the hierarchy constraints.

Why it’s separated from the architecture

VHDL deliberately splits “what” (entity) from “how” (architecture):

• An entity can have multiple architectures — one for behavioral simulation, another for synthesis, another for testbench wrappers. You pick which architecture to use at compile time.
• Top-level integration is easier — you can wire up entities by interface alone, before any internal logic is written.
• It mirrors hardware reality: a chip has fixed pins (entity) but the silicon inside (architecture) is a separate concern.

How a sub-block uses an entity

When a larger design wants to instantiate this block, it does so via the entity’s interface:

component example2 is
    port (
        x1, x2, x3, x4 : in  std_logic;
        f, g           : out std_logic
    );
end component;
-- ...
inst1: example2 port map (a, b, c, d, out_f, out_g);

The instance maps the parent’s signals to the entity’s ports.

Common patterns

For combinational logic blocks, the entity has only inputs and outputs of std_logic or std_logic_vector:

entity full_adder is
    port (a, b, cin : in  std_logic;
          sum, cout : out std_logic);
end entity full_adder;

For sequential blocks, the entity adds a clock and often a reset:

entity counter is
    port (clk, reset : in  std_logic;
          count      : out std_logic_vector(3 downto 0));
end entity counter;

For the implementation side, see VHDL architecture. For the broader language, see VHDL.