T flip-flop

A T flip-flop (“T” for toggle) has a single input $T$. On each clock edge, if $T=1$ the flip-flop toggles its output (flips $0\leftrightarrow 1$); if $T=0$, it holds.

$T$	$Q(t+1)$
0	$Q(t)$
1	$\overline{Q(t)}$

Implementation is a D flip-flop with $D=T\oplus Q$:

When $T=0$: $D=Q$, so $Q$ stays the same on the next clock edge. When $T=1$: $D=\overline{Q}$, so $Q$ flips.

The defining algebraic equation:

$D=T\overline{Q}+\overline{T}Q=T\oplus Q$

Where they’re useful

T flip-flops are awkward for general-purpose storage but excellent for one specific job: counters. A chain of T flip-flops with $T$ tied high produces a binary counter — each stage toggles at half the rate of the stage below it, giving a binary count sequence.

For an asynchronous up-counter, wire each $Q_i$ to the next stage’s clock input. The bits ripple — bit 0 toggles on every external clock; bit 1 toggles when bit 0 falls; bit 2 toggles when bit 1 falls. See Counter (digital) for the full structure.

For other purposes, T is generally inferior to D (which has cleaner semantics) or JK (which generalizes T’s toggle behavior).

Usage status

T flip-flops aren’t sold as standalone parts much anymore — synthesizers and libraries prefer to compose toggle behavior from D flip-flops with explicit XOR feedback. The T model is still useful for thinking about counter design, but in practice you’d describe the behavior in VHDL and let the tool generate the underlying gates.

The behavior is also a special case of the JK flip-flop: tying $J=K=T$ makes a JK flip-flop behave identically to a T flip-flop.