JK flip-flop

A JK flip-flop generalizes the SR latch by giving meaning to the previously-forbidden state ($J=K=1$): on that input it toggles, behaving like a T flip-flop.

$J$	$K$	$Q(t+1)$
0	0	$Q(t)$ (hold)
0	1	0 (reset)
1	0	1 (set)
1	1	$\overline{Q(t)}$ (toggle)

So $J$ acts like Set, $K$ acts like Reset, $JK$ together acts like Toggle, and $00$ holds. No forbidden states.

This four-row truth table is captured compactly by the JK characteristic equation:

$Q(t+1)=J\cdot \overline{Q(t)}+\overline{K}\cdot Q(t)$

You can verify each row by substitution: $J=K=0$ gives $Q(t)$, $J=0,K=1$ gives $0$, $J=1,K=0$ gives $1$, $J=K=1$ gives $\overline{Q(t)}$. The characteristic equation is the standard FSM specification of the device — you’ll see analogous equations for D ($Q(t+1)=D$) and T ($Q(t+1)=T\oplus Q(t)$).

Implementation as a D flip-flop with the right input expression:

$D=J\overline{Q}+\overline{K}Q$

Verifying:

• $J=K=0$: $D=0+Q=Q$ → hold.
• $J=0,K=1$: $D=0+0=0$ → reset.
• $J=1,K=0$: $D=\overline{Q}+Q=1$ → set.
• $J=K=1$: $D=\overline{Q}+0=\overline{Q}$ → toggle.

So JK is versatile: with the right $J,K$ wiring, it can mimic D, T, or SR behavior, all from the same physical flip-flop.

When to use it

JK is sometimes called a “universal” flip-flop because it can implement all the others by tying inputs:

• D behavior: $J=D$, $K=\overline{D}$.
• T behavior: $J=K=T$.
• SR behavior: $J=S$, $K=R$ (with $J=K=1$ now meaning toggle instead of forbidden — different semantics, but useful in some FSMs).

In practice, modern designs use D flip-flops almost exclusively — the synthesis tool maps any behavior you describe in VHDL onto D flip-flops with appropriate combinational logic. JK matters historically (it was popular in TTL designs of the 1970s–80s) and shows up in textbook problems but rarely in current engineering practice.

The downside of JK: two inputs instead of one means more wiring and more potential for input glitches when $J$ and $K$ both change near a clock edge.