Latch (digital)

A latch is the simplest type of digital storage element. It holds a single bit of state and is level-sensitive — its inputs can affect the output any time they’re applied, not just at clock edges. That distinguishes it from a flip-flop, which only updates on a clock edge.

A latch is built from a small piece of combinational logic arranged with a feedback loop, which is what gives it memory.

Basic SR latch

The simplest latch is the basic SR latch, formed from two cross-coupled NOR gates:

Two inputs ($S$ and $R$, for “set” and “reset”) and two outputs ($Q_a$ and $Q_b$, intended to be complements).

$S$	$R$	$Q_a$	$Q_b$	Behavior
0	0	previous $Q_a$	previous $Q_b$	hold (no change)
0	1	0	1	reset
1	0	1	0	set
1	1	0	0	forbidden

When both $S$ and $R$ are $0$, the latch holds whatever state it was in before — the feedback maintains it. The hold-row entries say “previous”: if the latch was previously set ($Q_a=1,Q_b=0$) it stays set; if previously reset ($Q_a=0,Q_b=1$) it stays reset. The truth table can’t write a single value here because the row’s behavior depends on history — that’s the whole point of a memory element. When $S=1$, $Q_a$ is forced to $1$ and $Q_b$ to $0$; when $R=1$, the opposite.

The $S=R=1$ case is the forbidden state: both outputs go to $0$, breaking the ”$Q_a$ and $Q_b$ are complements” invariant. Worse, when $S$ and $R$ both transition back to $0$ at the same time, the final state is unpredictable — a race condition in the gate delays decides which output settles to $1$. Don’t drive both inputs high simultaneously.

Basic latches respond to input changes immediately, with no clock control. That makes them fast but unsuitable for synchronous design where you want all storage updates to happen at well-defined moments.

Gated SR latch

A gated SR latch adds a clock (or enable) input that gates when $S$ and $R$ can affect the latch:

Two AND gates qualify $S$ and $R$ with the clock. When clock is $0$, $S^{\prime }=R^{\prime }=0$ and the latch holds its state regardless of the actual $S$ and $R$ inputs. When clock is $1$, the gated $S$ and $R$ pass through and the latch behaves like a basic SR latch.

Clk	$S$	$R$	$Q(t+1)$
0	x	x	$Q(t)$ (no change)
1	0	0	$Q(t)$ (no change)
1	0	1	0
1	1	0	1
1	1	1	x (forbidden)

The forbidden state is still there — gating $S$ and $R$ doesn’t fix the underlying problem of asserting both. The fix is the gated D latch.

Gated D latch

A gated D latch eliminates the forbidden state by tying $S=D$ and $R=\overline{D}$. The two are always complements, so the $S=R=1$ case is now impossible:

Clk	$D$	$Q(t+1)$
0	x	$Q(t)$
1	0	0
1	1	1

When clock is high, $Q$ follows $D$ — the latch is “transparent.” When clock is low, $Q$ holds its last value.

This transparency during the high phase of the clock is the defining property of a level-sensitive latch and is also its main weakness for synchronous design. Any change in $D$ during clock-high will propagate to $Q$ immediately, so chains of latches can glitch through more states than intended in a single clock cycle. The fix is to use edge-triggered flip-flops instead, which only sample the input at a clock edge.

See Level and Edge-Triggering for a side-by-side comparison.