NOR gate

A NOR gate outputs the complement of an OR: $1$ only when all inputs are $0$.

$f=\overline{x_1+x_2}$

$x_1$	$x_2$	$\overline{x_1+x_2}$
0	0	1
0	1	0
1	0	0
1	1	0

Drawn as an OR symbol with a bubble at the output.

CMOS implementation

A 2-input NOR mirrors a NAND gate structurally but with the networks swapped: 2 PMOS in series in the pull-up, 2 NMOS in parallel in the pull-down.

The pull-up chain conducts only when both PMOS are on — i.e., when both inputs are $0$ — pulling the output high. For any other combination, at least one NMOS in the pull-down is on, dragging the output low.

In silicon NOR is slower than NAND for the same logic depth, because the series PMOS chain has more resistance than a series NMOS chain (holes are slower charge carriers than electrons). When designers have a choice, they prefer NAND-based logic. NOR shines when the natural expression of a function lends itself to it — like the cross-coupled latch, which is built from two NORs.

Universality

NOR is also a universal gate — any Boolean function can be built from NOR alone, just like NAND.

Conversions:

• NOT: $\overline{x+x}=\overline{x}$.
• OR: NOR followed by NOR-as-NOT: $(x\text{ NOR }y)\text{ NOR }(x\text{ NOR }y)=x+y$.
• AND: invert both inputs via NOR-as-NOT, then NOR: $(x\text{ NOR }x)\text{ NOR }(y\text{ NOR }y)=\overline{\overline{x}+\overline{y}}=xy$ by De Morgan’s Laws.

NOR-NOR synthesis

Dual to NAND-NAND synthesis. Convert a POS expression to an all-NOR implementation:

1. Write $f$ in POS form.
2. Apply double negation and push the inner negation into the AND using De Morgan’s Laws — each OR term becomes the NOR of its literals, and the outer AND becomes a final NOR.

Useful identities:

• $a\cdot b=\overline{\overline{a}+\overline{b}}=\overline{a}\text{ NOR }\overline{b}$ — AND by NOR-ing the inverted inputs (De Morgan).
• $a+b=\overline{a\text{ NOR }b}=(a\text{ NOR }b)\text{ NOR }(a\text{ NOR }b)$ — recover an OR by inverting a NOR.
• $a\cdot b=(a\text{ NOR }a)\text{ NOR }(b\text{ NOR }b)$ — AND built entirely from NOR, using NOR-as-NOT to invert each input first.

Pick NAND-NAND for SOP-style designs and NOR-NOR for POS-style designs. Either works for any function; the difference is which form has fewer terms after minimization.