CMOS

CMOS (Complementary MOS) is a logic family that uses both NMOS and PMOS transistors arranged so the output is always actively driven and never draws steady-state current. Every CMOS gate has two halves: a pull-up network (PUN) of PMOS transistors that connects the output to $V_{DD}$ when the function should be $1$, and a pull-down network (PDN) of NMOS transistors that connects the output to ground when the function should be $0$.

Critically, the two networks are complementary: for any input combination, exactly one of them is conducting and the other is off. That means there’s never a path from $V_{DD}$ to ground through the gate (no static current), and the output is always tied to either supply or ground (no floating outputs).

The two networks

The PUN and PDN are dual graphs: each network is built from the same input variables, but with the topology swapped — every series connection in one network becomes a parallel connection in the other, and vice versa. Each network expresses, by its conduction condition, the function it pulls toward:

• The PDN’s conduction condition is the function that the gate should drive low. If the PDN conducts when $A\cdot B=1$, the gate output goes low when $A\cdot B=1$.
• The PUN’s conduction condition is the function that the gate should drive high. By De Morgan’s laws applied to the dual graph, the PUN conducts exactly when the PDN does not.

So if the PDN is ”$x_1$ AND $x_2$” (two NMOS in series), the PUN is ”$\overline{x_1}$ OR $\overline{x_2}$” (two PMOS in parallel — the dual graph). When $x_1=x_2=1$, both NMOS conduct and pull the output low; both PMOS are off so the pull-up disconnects. For any other input combination, the NMOS chain is broken and at least one PMOS conducts, pulling the output high. This is exactly a NAND gate.

The mnemonic: in either network, stacked → AND’ed, parallel → OR’ed describes that network’s conduction condition. Because the gate output is the complement of the PDN’s conduction (and equals the PUN’s conduction), stacked NMOS in the PDN gives a NAND output, not AND.

Why CMOS dominates

Three properties combined make CMOS the default for digital chips:

1. No static power. Steady-state current is essentially zero. Current flows mainly during switching, both to charge or discharge load capacitance and from a brief shoot-through when both networks momentarily conduct as the input crosses the threshold region. So a CMOS chip dissipates power roughly proportional to its switching activity, not to its size.

2. Strong output drive. Outputs are always pulled hard to a rail, giving full-rail swings ($0$ to $V_{DD}$) and excellent noise margins.

3. Symmetric switching. With matched PUN and PDN, rise times and fall times are similar.

The price is that you need both transistor types, which costs silicon area. A CMOS NAND has 4 transistors; an equivalent NMOS-only ratio’d circuit would have 2 plus a load resistor, but that resistor wastes power continuously. The trade-off is worth it.

Building gates from PUN/PDN

To design a CMOS gate for a given function $f$:

1. Write $f$ in SOP form — that’s what the PUN naturally implements.
2. The PDN implements $\overline{f}$ — derive it via De Morgan’s Laws from the PUN, replacing series with parallel and vice versa.
3. NMOS goes in the PDN, PMOS in the PUN. Inputs feed both networks.

The result: a direct AND in CMOS is awkward (the natural pull-down is NMOS in series, which inverts the function), so AND is normally built as NAND-then-NOT. Same with OR (NOR-then-NOT). The “natural” CMOS gates are NOT, NAND, and NOR — and from those everything else.

Gate (n-input)	CMOS transistors
NOT	2 (1 PMOS, 1 NMOS)
NAND	$2n$
NOR	$2n$
AND	$2n+2$ (NAND + NOT)
OR	$2n+2$ (NOR + NOT)
XOR	~8
XNOR	~10

XOR and XNOR are expensive in CMOS, which is why arithmetic circuits like adders try to use them sparingly. [Note: this specific claim is from general knowledge and hasn’t been independently verified.] The exact transistor counts for XOR/XNOR depend on the implementation style (static CMOS, transmission-gate, pass-transistor) and are commonly quoted as 8–12.

Fabrication note (Electronics I)

“Complementary” is also a statement about silicon: CMOS builds both complementary device types — n- and p-channel MOSFETs — on a single chip. The n-MOSFETs sit directly in the common p-type substrate, while the p-MOSFETs are fabricated inside isolated n-type wells (n-wells) diffused into that substrate, so each transistor type has the substrate polarity it needs.