Static RAM (SRAM) is volatile memory built from a 6-transistor flip-flop per cell. Each cell holds its bit as long as power is supplied, no refresh needed, hence “static.”
SRAM is the fast, expensive end of the Memory hierarchy. Used for processor registers, on-chip cache (L1, L2, L3), and high-speed external memories where speed matters more than cost.
Properties
- Cell: 6 transistors, a cross-coupled pair of inverters plus two access transistors.
- Speed: ~ to ns access.
- Density: low compared to DRAM. 6 transistors per bit limits how many bits fit on a chip.
- Cost per bit: high.
- Volatile: data is lost when power goes off.
- No refresh: the cell holds its state as long as Vdd is supplied.
Why 6 transistors
A pair of cross-coupled inverters forms a bistable element: two stable states (Q = 0 or Q = 1), and external “noise” smaller than half the supply can’t flip it. Each inverter is 2 transistors (an NMOS and PMOS in CMOS), so the storage core is 4 transistors. Add 2 more as access switches that connect the cell to the bit lines during read or write.
Total: 6 transistors per bit.
The bistable design is what makes SRAM fast (no waiting for a capacitor to charge or discharge) and immune to leakage (the cross-coupled inverters actively drive the bit lines).
Address pin count
SRAM chips have one address pin per address bit, so the entire address goes to the chip at once. Contrast DRAM, which multiplexes addresses in two halves to save pins.
For a SRAM chip ( bytes), 17 address pins. Plus 8 data pins, plus power, ground, chip select, output enable, write enable: around 30 pins on the package, manageable for the kind of single-cycle bus a small RISC core can drive directly.
Non-multiplexed addressing keeps SRAM simple to use. No row/column timing protocols, no refresh controller.
Worked example: 128K × 8 SRAM organization
Capacity: bits KB.
Memory cell array: physically arranged as a array of cells (1 Mbit total).
Of the 17 address bits:
- Upper 10 bits → decode to one of rows.
- Lower 7 bits → select one of groups of 8 cells within the row.
So each row holds bits, matching the column count. One row contains the data for 128 consecutive byte-addressable locations.
Use cases
SRAM shows up wherever speed matters more than capacity:
- Processor registers, the fastest tier. Architectural register files are usually built from multi-ported SRAM cells (8T, 10T, or more), not the standard 6T cell above. The extra transistors give the cell several independent read or write ports, so multiple instructions can touch registers in the same cycle. The 6T cell is single-ported and would bottleneck a wide superscalar pipeline.
- L1, L2, L3 caches: on-chip SRAM, hit times from ns (L1) to ns (L3).
- TLBs: small SRAM tables for fast address translation.
- External SRAM: fast scratch memory in embedded systems, packet buffers in network routers, video memory in old game consoles.
For bulk storage you’d never use SRAM. Too expensive per bit, too power-hungry, too low-density. That’s where DRAM takes over.