Idriss Rami — Notes

General-purpose registers

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General-purpose registers (GPRs) are the small, fast on-chip storage locations the processor uses for operands and results. They’re the top of the Memory hierarchy — even faster than on-chip cache. Most arithmetic and logical instructions operate on registers, not memory directly.

A processor typically has 16 to 32 general-purpose registers, each holding one word (32 or 64 bits). Together they form the register file, the storage block that the datapath reads from and writes to in every instruction cycle.

Why registers exist

A modern processor runs at gigahertz speeds. A register access takes a fraction of a nanosecond. The next stop isn’t main memory directly — there’s a multi-level cache between them. L1 cache is ~1 ns, L2 ~5–10 ns, L3 ~20–40 ns, and main DRAM only ~100 ns. So in the worst case (a cache-cold load), you’re paying 100 ns; on a typical L1 hit, an order of magnitude less. Even the cheapest cache hit is much slower than touching a register, which is why registers are still essential — but the “registers vs main memory” framing skips the layers in between.

Registers solve this by holding actively-used values right next to the ALU. A typical sequence:

  1. Load a few values from memory (or, more commonly, cache) into registers — slow on a cache miss, fast on a hit.
  2. Do many arithmetic operations entirely on those registers — fast.
  3. Store the final results back to memory — eventually reaches DRAM, possibly via the cache hierarchy.

This is the “load/store architecture” of RISC machines — see Basic Operational Concepts.

Naming and special registers

Conventionally numbered . Some are reserved for specific purposes:

  • R0 (or r0 in Nios II) — often hardwired to zero (especially in RISC ISAs). Reading it always returns 0; writing has no effect. Useful as a constant source.
  • Stack pointer (SP) — points to the top of the stack. sp (alias for r27) in Nios II.
  • Frame pointer (FP) — stable reference within a stack frame for accessing parameters and local variables. fp (alias for r28) in Nios II.
  • Return address / link register (LR) — holds the return address for the currently executing subroutine. ra (alias for r31) in Nios II.
  • Status register / processor status — holds flags like Z, N, C, V plus interrupt-enable. Sometimes considered separate from the general-purpose set.

The remaining registers are free for the program to use. Calling conventions specify which registers a subroutine must preserve and which the caller is responsible for saving — see Subroutine linkage.

Register file in the datapath

In the Hardware datapath, the register file has:

  • Two read ports (A and B) — read two registers simultaneously, indexed by addresses from the IR.
  • One write port (C) — write one register per cycle, indexed by another field of the IR, gated by the RF_Write control signal.

This means a single instruction can read two operands and write one result in the same cycle. Adding a third read port (for instructions like cmp R1, R2, R3 that read three) is possible but doubles the read-port complexity.

Why “general-purpose”

Distinguishes from special-purpose registers like PC, IR, and the various inter-stage registers (RA, RB, RZ, RY, RM in the datapath). Those are part of the implementation — the programmer can’t access them. The general-purpose registers are part of the ISA — the programmer reads/writes them by name in every instruction.

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