The instruction set architecture (ISA) is the contract between hardware and software: the complete specification of what instructions a processor understands, what registers are visible, what addressing modes exist, and how memory is laid out. Two CPUs with the same ISA run the same binaries, even if their internal organization differs wildly.
ISA is the key abstraction in computer architecture. It’s specified independently of any particular implementation — once you know the ISA, you can write programs that any conforming chip can run.
What an ISA defines
- Instructions and their encodings — the bit patterns that represent operations like
add,load,branch, etc. - Registers — how many GPRs, their sizes, special-purpose registers like PC and IR.
- Addressing modes — how operands are computed (immediate, register, base+offset, indirect, indexed, etc.).
- Memory model — Byte addressability, Endianness, Word alignment requirements.
- Exception/interrupt model — how the processor responds to faults and external events.
- Privilege levels — user vs. kernel mode, if applicable.
RISC vs CISC
Two main design philosophies:
RISC — Reduced Instruction Set Computer
- Simple, fixed-length instructions — every instruction is the same size (typically 32 bits), making decoding fast and parallel.
- Load/store architecture — only
loadandstoreaccess memory. All arithmetic operates on registers. - Large register file — 32+ general-purpose registers reduce memory traffic.
- Most instructions complete in one cycle — predictable timing makes pipelining straightforward.
- Compiler-driven — the compiler is expected to do the optimization work; the hardware stays simple.
Examples: ARM, MIPS, RISC-V, Nios II. Modern dominant style.
CISC — Complex Instruction Set Computer
- Variable-length instructions — some are 1 byte, others up to 15+ bytes. Decoding is more complex.
- Memory-to-memory operations allowed — instructions can directly use memory operands without separate loads.
- Fewer registers — the original x86 had only 8 general-purpose registers.
- Multi-cycle instructions — some instructions (string copy, division, BCD adjust) take many cycles.
- Rich addressing modes — auto-increment, scaled-indexed, segment+offset, etc.
Examples: x86, x86-64 (descended from CISC but internally translated to RISC-like micro-ops). VAX (canonical CISC, now historical).
The line has blurred. Modern x86 chips internally translate CISC instructions into simpler micro-ops and execute them with RISC-style pipelining. The 32-bit ARM family accumulated complex instructions over the years (load/store multiple, conditional execution on most instructions, Thumb modes), though AArch64 (ARMv8 64-bit) deliberately removed many of those oddities and is closer to a clean RISC. The pure RISC vs CISC debate is largely historical.
RISC design principles
RISC tries to make instructions:
- Operate on registers (load/store memory access only).
- Use simple addressing modes.
- Be the same length.
- Complete in one cycle.
These all serve a single goal: make the hardware simple enough that you can pipeline aggressively and clock fast.
ISA topics worth their own notes
The ISA touches almost every architectural concept:
- Instruction execution cycle — the fetch/decode/execute loop.
- Hardware datapath — what hardware actually runs the instructions.
- Memory address, Byte addressability, Endianness, Word alignment — memory model.
- Stack (computing), Subroutine, Subroutine linkage — function call conventions.
- O, Interrupt service routine — exception handling.
- Register transfer notation — how to describe instruction behavior precisely.
- Nios II assembly language — one specific ISA used as the running example in Computer Architecture.
For the actual list of Nios II instructions, see Nios II data-movement instructions, Nios II arithmetic instructions, Nios II branch instructions, Subroutine (for call/ret).