Idriss Rami — Notes

Instruction Set Architecture

3 min read

The instruction set architecture (ISA) is the contract between hardware and software: the full spec of what instructions a processor understands, what registers are visible, what addressing modes exist, and how memory is laid out. Two CPUs with the same ISA run the same binaries even if their internal organization differs wildly.

It’s the abstraction in computer architecture, specified independently of any particular implementation. Once you know the ISA you can write programs that any conforming chip will run.

What an ISA defines

  • Instructions and their encodings: the bit patterns for operations like add, load, branch.
  • Registers: how many GPRs, their sizes, special-purpose registers like PC and IR.
  • Addressing modes: how operands are computed (immediate, register, base+offset, indirect, indexed, etc.).
  • Memory model: Byte addressability, Endianness, Word alignment requirements.
  • Exception/interrupt model: how the processor responds to faults and external events.
  • Privilege levels: user vs. kernel mode, if applicable.

RISC vs CISC

Two main design philosophies:

RISC — Reduced Instruction Set Computer

  • Simple, fixed-length instructions: every instruction is the same size (typically 32 bits), so decoding is fast and parallel.
  • Load/store architecture: only load and store touch memory. All arithmetic operates on registers.
  • Large register file: 32+ GPRs cut memory traffic.
  • Most instructions complete in one cycle, so timing is predictable and pipelining is straightforward.
  • Compiler-driven: the compiler does the optimization work, the hardware stays simple.

Examples: ARM, MIPS, RISC-V, Nios II. Modern dominant style.

CISC — Complex Instruction Set Computer

  • Variable-length instructions: some are 1 byte, others up to 15+ bytes, so decoding is more complex.
  • Memory-to-memory operations allowed: instructions can use memory operands directly without separate loads.
  • Fewer registers: the original x86 had only 8 GPRs.
  • Multi-cycle instructions: string copy, division, BCD adjust take many cycles.
  • Rich addressing modes: auto-increment, scaled-indexed, segment+offset, etc.

Examples: x86, x86-64 (descended from CISC but internally translated to RISC-like micro-ops). VAX (canonical CISC, now historical).

The line has blurred. Modern x86 chips translate CISC instructions internally into simpler micro-ops and run them with RISC-style pipelining. The 32-bit ARM family accumulated complex instructions over the years (load/store multiple, conditional execution on most instructions, Thumb modes), though AArch64 (ARMv8 64-bit) dropped many of those oddities and is closer to a clean RISC. The pure RISC vs CISC debate is mostly historical now.

RISC design principles

RISC tries to make instructions:

  • Operate on registers (load/store memory access only).
  • Use simple addressing modes.
  • Be the same length.
  • Complete in one cycle.

All of these serve one goal: keep the hardware simple enough to pipeline aggressively and clock fast.

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