NMOS transistor

An NMOS transistor (N-channel Metal-Oxide-Semiconductor field-effect transistor) is a switch controlled by a voltage on its gate. The actual turn-on condition is

$V_{GS}>V_{tn}$

where $V_{GS}=V_G-V_S$ is the gate-to-source voltage and $V_{tn}$ is the threshold voltage of the NMOS (typically $0.3$–$0.7\text{V}$ in modern processes, positive). When $V_{GS}$ exceeds $V_{tn}$, an inversion layer of electrons forms under the gate and connects the drain to the source — the channel conducts. Below $V_{tn}$, the channel is essentially off (sub-threshold leakage exists but is exponentially small).

In digital logic the gate is driven to either $0\text{V}$ (off) or $V_{DD}$ (on), with $V_{DD}$ chosen well above $V_{tn}$. So as a switch model: gate high → conducting, gate low → open.

This is why NMOS sits in the pull-down network of a CMOS gate: it pulls the output low when its gate is driven high. It’s the natural switch for “this output should be $0$ when this input is $1$.”

The three terminals are source, gate, and drain. Source $V_S$ is where charge carriers (electrons, in NMOS) enter the channel. Gate $V_G$ controls whether the channel conducts. Drain $V_D$ is where carriers leave. NMOS conventionally has $V_S$ tied to ground.

Threshold drop (“weak 1”)

Because the turn-on condition is $V_{GS}>V_{tn}$, an NMOS used to pass a high signal degrades it: as the source voltage rises toward the gate, $V_{GS}$ shrinks. Once $V_S$ reaches $V_{DD}-V_{tn}$, $V_{GS}$ has fallen to exactly $V_{tn}$ and the channel cuts off. The output settles at $V_{DD}-V_{tn}$ rather than $V_{DD}$ — a “weak 1.” This is why CMOS uses PMOS in the pull-up network and reserves NMOS for pulling low (where it produces a “strong 0”). It’s also why pass-transistor logic typically uses transmission gates (NMOS in parallel with PMOS) rather than bare NMOS pass transistors.

Pair an NMOS with a PMOS transistor of the opposite polarity and you get a CMOS gate that draws no static current.

Physical structure and analog operation (Electronics I)

Physically an n-MOSFET is built in a p-type substrate with two heavily-doped n+ regions forming the source and drain. Raising the gate above $V_{tn}>0$ inverts the surface into an electron MOSFET channel connecting source to drain (see channel formation). The same device that acts as a digital pull-down switch is biased in the MOSFET saturation region for analog work, where its square-law current makes it the gain element of a Common-source amplifier. So an n-MOSFET is not just a switch — in saturation it is the workhorse analog transistor.