The gate input cost (GIC) is a simple measure of a circuit’s complexity: count every input pin to every gate in the implementation. A 3-input AND gate contributes ; a 2-input OR contributes ; a NOT contributes . Sum over all gates and you have the GIC.
The point is to compare two equivalent expressions: the one with lower GIC needs fewer wires and fewer transistors, so it’s smaller, faster, and cheaper.
GIC counts both the number of gates and the number of inputs to each. A 4-input AND has GIC , while two 2-input ANDs cascaded have GIC also (two pairs of inputs). The cost of “fan-in 4” and “two stages of fan-in 2” can be the same — but the latter has more gates and more propagation delay.
Computing from an expression
For a SOP or POS expression, GIC is the sum of:
- Every literal appearance (each contributes — it’s an input to a gate somewhere).
- The number of distinct complemented literals (each requires a NOT, contributing ).
- The number of non-literal terms (each is a gate that has multiple inputs feeding it).
Worked example. :
- 5 literals total: .
- 1 complemented literal (), so for the inverter.
- 3 non-literal terms: , , .
GIC .
Costs of common gates
For comparing minimization choices, useful baselines:
- NAND, NOR: equivalent GIC of (the gate plus an inverter).
- XOR, XNOR: equivalent GIC of — they’re expensive to build, so minimization rarely benefits from introducing them.
- AND, OR: for an -input gate.
- NOT: .
This is why most minimization stops at AND/OR/NOT and only uses XOR when the function naturally calls for it (parity, addition).
GIC is one cost metric among several. Others include literal count alone (cheaper to compute, ignores gate structure), transistor count (more accurate physically), and gate delay (counts levels rather than inputs). Use GIC when you want a quick, structural complexity number to drive a minimization choice.