Idriss Rami — Notes

Processor Status (PS) register

3 min read

The processor status register (PS, sometimes PSR or just “status”) is a special-purpose register holding flags that describe the processor’s current operating state. Most importantly: it includes the interrupt enable (IE) bit that masters whether interrupts can fire.

PS contains:

  • IE — Interrupt Enable. When 1, interrupts can fire. When 0, all interrupts are blocked at the processor level (regardless of device-level enables).
  • Condition flags (on processors that have them) — N, Z, C, V from the most recent ALU operation.
  • Privilege/mode bits — user vs. kernel mode in OSes that use protection.
  • Other architecture-specific bits — endianness mode, FPU enable, etc.

In Nios II, the equivalent is the status control register, accessed via rdctl and wrctl instructions.

What happens to PS during an interrupt

When an interrupt fires:

  1. Hardware saves the current PS into a separate register (often called IPS for “Interrupted PS” or estatus in Nios II).
  2. Hardware clears the IE bit in PS — so the ISR can’t be immediately re-interrupted by the same source.
  3. The ISR runs.
  4. The return-from-interrupt instruction restores PS from IPS — which restores IE to its original value.

The save-and-restore protects the ISR from interrupting itself, while still allowing the original IE state to come back when the ISR is done.

Why save IE rather than just leave it cleared?

Because the interrupted program might have had IE set or cleared for its own reasons. If the ISR cleared IE on entry and forgot to restore it, the interrupted program would be running with interrupts off — slowing or breaking everything.

Restoring PS on return-from-interrupt is the correct way: whatever IE was when the interrupt fired, it’s that again on return.

Manipulating PS

The processor doesn’t access PS the same way as a general-purpose register. Special instructions handle it.

The MoveControl syntax used in the Hamacher textbook (and elsewhere in this vault) is pedagogical — a generic pseudo-instruction the textbook uses to describe the operation. It’s not a real instruction in any standard ISA, so don’t search vendor docs for it. The real per-architecture forms:

  • Nios II: rdctl r2, status (read), wrctl status, r2 (write).
  • ARM Cortex-M: MRS r2, PRIMASK / MSR PRIMASK, r2 (interrupt-mask), or the dedicated CPSIE i / CPSID i for global enable/disable.
  • x86: STI / CLI for the interrupt flag specifically; PUSHF / POPF to read/write the whole EFLAGS register.

Use MoveControl as shorthand only inside textbook-style examples; in real code, look up the equivalent for your target.

To enable interrupts globally:

MoveControl R2, PS
Or R2, R2, #1            ; set IE bit
MoveControl PS, R2

Disabling is similar with an AND-NOT pattern.

In context

PS is one piece of the interrupt mechanism. To actually receive interrupts from a specific device, three enable bits must all be on:

  1. Device’s interrupt enable (in its CONTROL register) — see I-O device interface.
  2. Per-source enable in the processor (IENABLE register) — controls which IRQ lines reach the processor.
  3. Master interrupt enable in PS (the IE bit) — global on/off.

Each level can selectively block interrupts. The IE bit in PS is the lowest-overhead way to disable everything when, say, you’re in the middle of a critical section that mustn’t be interrupted.

Graph View

Backlinks