Synchronous DRAM (SDRAM) is a DRAM variant that synchronizes its operations with an external clock signal. Unlike asynchronous DRAM, where the Memory controller had to drive every step of a read or write transaction explicitly, SDRAM advances internal state machines automatically on each clock edge. That buys you burst transfers: read a stream of consecutive addresses with one command, and the chip streams the data on consecutive clock edges.
SDRAM has displaced asynchronous DRAM almost entirely. Modern computers use SDRAM (and its DDR variants) for main memory.
Why a clock helps
In asynchronous DRAM:
- Memory controller asserts row address with RAS.
- Memory controller waits a precise time, then asserts column address with CAS.
- Memory controller waits another precise time, reads data.
- Memory controller deasserts everything.
Each step has fixed timing requirements. If the controller misses by even a few nanoseconds, the operation fails. The controller is constantly busy managing one access.
SDRAM eliminates the explicit timing management:
- Memory controller issues a “read” command on a clock edge with the row+column address.
- After a fixed number of clock cycles (the “CAS latency”), the chip begins outputting data.
- On each subsequent clock edge, the chip outputs the next consecutive word.
The controller can issue another command while data is still streaming; the chip’s internal state machine handles the transfer.
Burst transfers
SDRAM can output many consecutive words per command. A typical burst length is 4 or 8.
For a workload that reads a cache line (typically 64 bytes = 16 32-bit words on a 32-bit bus, or 8 64-bit words on a 64-bit bus), one burst transfers the whole line. The setup overhead (address decode, row activation) is amortized across the whole burst.
This matches modern processor cache behavior: caches always read full lines, never single words. SDRAM’s burst mode is built for exactly that.
DDR (Double Data Rate)
DDR SDRAM (and DDR2, DDR3, DDR4, DDR5) transfers data on both edges of the clock, rising and falling. So a 1 GHz clock yields 2 GT/s (giga-transfers per second) of bandwidth.
Each generation roughly doubles bandwidth and reduces voltage:
| Generation | Year | Voltage | Bandwidth (per channel) |
|---|---|---|---|
| DDR | 2000 | 2.5 V | ~3.2 GB/s |
| DDR2 | 2003 | 1.8 V | ~8 GB/s |
| DDR3 | 2007 | 1.5 V | ~17 GB/s |
| DDR4 | 2014 | 1.2 V | ~25 GB/s |
| DDR5 | 2020 | 1.1 V | ~50 GB/s |
Lower voltage helps power efficiency in laptops and datacenters; higher bandwidth keeps multi-core CPUs fed.
Internal organization
SDRAM has multiple internal banks that can operate in parallel. While one bank is busy with a burst transfer, the controller can issue commands to other banks, so the chip is always making progress somewhere.
Modern DDR4 and DDR5 chips have 16+ banks per device.
Module labels like “DDR4-3200” encode the protocol and the transfer rate: DDR4 fixes the voltage and timing rules, 3200 MT/s means a 1.6 GHz I/O clock with transfers on both edges. The motherboard’s memory controller has to support the named generation, and DDR3, DDR4, DDR5 modules are keyed differently so you can’t physically mix them.