A programmable logic device (PLD) is a general-purpose chip whose internal logic is configured after manufacturing, by programming it, rather than fixed by the silicon mask. The user provides logic equations or a netlist; the chip’s programmable connections are set to implement them.
The two early flavors of PLD are the PLA and the PAL. They share a structure: a layer of AND gates produces product terms from the inputs and their complements, then a layer of OR gates combines those product terms into outputs. They differ in which layer is programmable.
PLA: Programmable Logic Array
A PLA has both planes programmable: the AND plane and the OR plane.
Inputs and their complements feed every AND gate via a programmable crosspoint matrix. The user picks which inputs feed which AND gates to form any product term. Then the products feed every OR gate via a second programmable matrix, picking which products go into each output.
The flexibility lets a PLA implement any SOP expression for multiple outputs, sharing common product terms across outputs (which saves area when several outputs use overlapping logic). The cost is silicon: two large programmable arrays.
PAL: Programmable Array Logic
A PAL is a stripped-down PLA: only the AND plane is programmable. Each OR gate has a fixed set of product terms allocated to it.
That gives up sharing but is much cheaper to manufacture and faster (one less programmable layer of fuses or transistors to traverse). A PAL works well when each output’s logic is small and independent, typical glue logic.
When you’d reach for these
PLAs and PALs predate FPGAs and have been mostly displaced by them for medium-to-large designs. Simple PLDs (GAL chips and small CPLDs, which are clusters of GAL-style macrocells with interconnect) still ship today for low-cost glue logic, board-level signal routing, and tiny embedded controllers where an FPGA would be overkill on cost, power, or boot time. The conceptual structure (AND plane → OR plane = SOP) still matters because it’s the mental model for LUTs in modern FPGAs.